code::perl::fixing bit blasted instances of modules in verilog

Some EDA tools have the bad habit of mangling the port names. For instance have a look at submodule2 in Snippet 1 below. The instance in top module has the ports converted from x, y to \x(1), \x(0), \y(2), ... etc.

Snippet 1:
module top;
submodule1 x1 (.\a(1) (net1), .\a(0) (net2));
submodule2 x2 (.\x(1) (x2), .\y(0) (x1) ,.\x(0) (1'b1), .\y(1) (\net=+123), .\y(2) (1'bz) ) ;
endmodule

//
module submodule1 (\a(1) ,\a(0) );
input \a(1) ;
input \a(0) ;
endmodule

//
module submodule2 (x , y);
input [1:0] x;
output [2:0] y;
endmodule


The perl script in Snippet 3, will convert the netlist from Snippet 1 to the one in Snippet 2.

But beware, see what happened to submodule1. If your netlist already has mangled ports but matched at both instance and entity levels, then this script will break the netlist. However this is rarely the case, so use it, but at your own risk.

Snippet 2:
module top;
submodule1 x1 ( .a ({net1 ,net2 }));
submodule2 x2 ( .y ({1'bz ,\net=+123 ,x1 }), .x ({x2 ,1'b1 })) ;
endmodule

//
module submodule1 (\a_1_ ,\a_0_ );
input \a_1_ ;
input \a_0_ ;
endmodule

//
module submodule2 (x , y);
input [1:0] x;
output [2:0] y;
endmodule

Snippet 3:
#!/usr/local/bin/perl

($#ARGV == 0 ) || die "Usage:fixBitBlastInstances.pl \nStopped";

open(FILEIN,$ARGV[0]);
open(FILEOUT,'>temp.v');

@lines = ;
close(FILEIN);
$text = "@lines";
$text =~ s/(\\\w+\S*)\((\d+)\)/\1_\2_/g;
@instances = split(/;/,$text);

for ($i= 0;$i != $#instances;$i++)
{ if ($instances[$i] =~ /\.\\\w+_\d+_/ )
{
$inst2proc = $instances[$i];
$inst2print = "";
%$pinlist = ();
while ($inst2proc =~ /\.\\(\w+)_(\d+)_\s+\((\S*?)\)\s*,?/)
{
$inst2print .= $`;
$inst2proc = $';
$pinlist->{$1}->[$2] = "$3";
}
print FILEOUT "$inst2print ";
@temparray = keys(%$pinlist);
$lastpin = pop @temparray;
foreach $pin (keys(%$pinlist)){
print FILEOUT ".$pin ({";
$k=scalar(@{$pinlist->{$pin}});
for($j=$k-1;$j >= 0; $j--) {
print FILEOUT "$pinlist->{$pin}->[$j] ";
if($j)
{print FILEOUT " ,";}
else
{print FILEOUT " })";}
}
if (($inst2proc =~ /\w+/)||($pin ne $lastpin)) {print FILEOUT ", ";}
}
print FILEOUT "$inst2proc;"
}
else
{ print FILEOUT "$instances[$i];"; }
}

print FILEOUT "\nendmodule";
close(FILEOUT);

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