sub 45 nm

Notes to self to remember what Intel did to scale sub 45nm:

• Changed the gate insulator from SiO2 to a high-k dielectric (reported to be a Hafnium based material), permitting greater thickness of the insulator material without weakening the field.
• Changed the manufacturing step for gate insulator creation from "reactive sputtering and metal organic chemical vapor deposition" to the "atomic layer deposition" which lets create smoother layers of deposits without leaving gaps in between.
• Replaced the polysilicon gate electrode with a metal one, which due to its higher electron density prevented phonons (vibrations of crystal lattice) from the high-k dielectric from propagating in the channel and hampering its charge carrier mobility.
  
• Separate metal based materials used for the creation of gate electrode for PMOSes and NMOSes. This is a key research outcome at Intel whose details have not been divulged. The manufacturing process also saw a change with a "gate last" approach.
  

Another key conclusion for the 45nm process is that the high performance and low leakage differentiation will significantly deepen. This will foster in some innovative methods in cell library development and automated synthesis of circuits from HDL.