The delta cycle funda

1 2 `timescale 1 ns/ 1 ps 3 4 5 module top(); 6 delta_cycle_verilog U1(); 7 delta_cycle_vhdl U2(); 8 endmodule 9 10 11 12 module delta_cycle_verilog( ); 13 14 reg [3:0] ff1_d, ff1_q, ff2_q ; 15 reg clk0, reset; 16 17 //Stimuli 18 19 initial 20 begin 21 clk0 <= 1'b0; 22 ff1_d <= 4'b0; 23 reset <= 1'b1; 24 #3; 25 reset <= 1'b0; 26 #30; 27 $stop; 28 end 29 30 always 31 #4 clk0 <= ~clk0; 32 33 always @ (posedge clk0) 34 #1 ff1_d <= ff1_d + 1'b1; 35 36 //Circuit 37 38 assign #0 clk1 = clk0; 39 assign #0 clk2 = clk1; 40 assign #0 clk3 = clk2; 41 assign #0 clk4 = clk3; 42 assign #0 clk5 = clk4; 43 44 always @ (posedge clk0, reset) 45 begin : FF1 46 if (reset == 1'b1) 47 ff1_q <= 4'b0000; 48 else 49 ff1_q <= ff1_d; 50 end 51 52 53 always @ (posedge clk5, reset) 54 begin : FF2 55 if (reset == 1'b1) 56 ff2_q <= 4'b0000; 57 else 58 ff2_q <= ff1_q; 59 end 60 61 endmodule 62

1 library IEEE; 2 use IEEE.std_logic_1164.all; 3 use IEEE.std_logic_unsigned.all; 4 5 entity delta_cycle_vhdl is 6 end entity; 7 8 architecture behav of delta_cycle_vhdl is 9 10 signal clk0, clk1, clk2, clk3, clk4, clk5, reset : std_logic:='0'; 11 signal ff1_d, ff1_q, ff2_q : std_logic_vector(3 downto 0):= "0000"; 12 13 begin 14 15 -- Stimuli 16 process is 17 begin 18 reset <= '1'; wait for 3 ns; 19 reset <= '0'; wait; 20 end process; 21 22 process is 23 begin 24 clk0 <= '0'; wait for 4 ns; 25 clk0 <= '1'; wait for 4 ns; 26 end process; 27 28 process (clk0) is 29 begin 30 if clk0'event and clk0 = '1' then 31 ff1_d <= (ff1_d + 1) after 1 ns; 32 end if; 33 end process; 34 35 -- Circuit 36 37 clk1 <= clk0; 38 clk2 <= clk1; 39 clk3 <= clk2; 40 clk4 <= clk3; 41 clk5 <= clk4; 42 43 ff1: process (clk0, reset) is 44 begin 45 if (reset = '1') then 46 ff1_q <= "0000"; 47 elsif clk0'event and clk0 = '1' then 48 ff1_q <= ff1_d; 49 end if; 50 end process; 51 52 ff2: process (clk5, reset) is 53 begin 54 if (reset = '1') then 55 ff2_q <= "0000"; 56 elsif clk5'event and clk5 = '1' then 57 ff2_q <= ff1_q; 58 end if; 59 end process ; 60 61 end architecture behav; 62

sub 45 nm

Notes to self to remember what Intel did to scale sub 45nm:

• Changed the gate insulator from SiO2 to a high-k dielectric (reported to be a Hafnium based material), permitting greater thickness of the insulator material without weakening the field.
• Changed the manufacturing step for gate insulator creation from "reactive sputtering and metal organic chemical vapor deposition" to the "atomic layer deposition" which lets create smoother layers of deposits without leaving gaps in between.
• Replaced the polysilicon gate electrode with a metal one, which due to its higher electron density prevented phonons (vibrations of crystal lattice) from the high-k dielectric from propagating in the channel and hampering its charge carrier mobility.
  
• Separate metal based materials used for the creation of gate electrode for PMOSes and NMOSes. This is a key research outcome at Intel whose details have not been divulged. The manufacturing process also saw a change with a "gate last" approach.
  

Another key conclusion for the 45nm process is that the high performance and low leakage differentiation will significantly deepen. This will foster in some innovative methods in cell library development and automated synthesis of circuits from HDL.